Semiconductor device technology continues to rapidly advance in the area of devices requiring setup and hold times for input signals. Specifically, dynamic random access memory (DRAM) technology has developed recently to reduce the dissociation of the operation speed between the microprocessor unit of the computer and the DRAM. In a DRAM, a predetermined clock signal is supplied to a clock input terminal. Synchronizing with this predetermined clock signal allows direct contact operation between the DRAM and the microprocessor.
High speed semiconductor parts necessitate relatively tight setup and hold time specifications for DRAMs. Due to the increasing operational speed of DRAMs, a relatively short setup/hold time window exists during which to sample an input signal (e.g., a row or column address strobe signal) in a DRAM. For example, a DRAM for a 125 MHZ microprocessor can have a 2 ns setup time and a 1 ns hold time specification. The inherent time delays in the circuit can cause the rising edge of a clock signal (or latching signal) to miss the setup/hold time window in the input signal, thus failing to enable the DRAM. Building a delay into the path traveled by the input signal can help delay the input signal to allow enough time for the clock signal to travel through the circuit.
Conventional DRAMs do not include any delay mechanism or delay circuit that can be adjusted after fabrication of the device to alter the amount of time the input signal is delayed. Therefore, these conventional DRAMs cannot adjust the setup/hold times to move the setup/hold time window to a point that can be utilized after the device is fabricated. This lack of ability to adjust the delay in the input signal path can result in fabrication of inoperable devices because of the relative difficulty in predicting the location of the input signal setup/hold time window prior to fabricating the device. Furthermore, as the speed of operation increases, the setup/hold time window will become increasing smaller, resulting in a greater number of inoperable devices.